1. Field of the Invention
The present invention relates to a semiconductor device.
2. Background Arts
U.S. Pat. No. 6,028,348B discloses an integrated circuit in which thermal resistance is reduced. The integrated circuit includes a transistor formed on an upper surface of a substrate, a ground surface provided on the transistor, a bonding pad provided on a back surface of the substrate, and a conductive via hole passing through the substrate to connect to the bonding pad.
In a field of wireless communication, a power amplifier capable of transmitting signals by large output is arranged in a final stage of a transmitter. Output of the transmitter depends on power and efficiency of the power amplifier. In order to improve the efficiency of the power amplifier, gallium arsenide (GaAs) or gallium nitride (GaN) having a high figure of merit is used as a material of a circuit element in high frequency bands, such as a microwave band or a millimeter-wave band. Simultaneously, in order to increase output of the power amplifier, a gate width of a field effect transistor (FET) is increased to increase an operating current, and a withstand voltage of the element is improved to raise an operating voltage.
As a structure of a device including the element formed on an insulated substrate, such as a GaAs FET and a GaN FET, an element structure in which a pattern that gives a reference potential is provided on a substrate back surface and a source of the FET is connected to the reference potential by a via hole passing through the substrate between the substrate back surface and the FET, is known. However, in the case of manufacturing the FET having a large gate width by a structure like this, the following problem arises.
For example, in the case of manufacturing an amplifier by a grounded source configuration, the via hole that connects the source of the FET and a back surface electrode and passes through the substrate has a significant length. In the microwave band and the millimeter-wave band, a conductor having a significant length behaves as an inductance. Thus, an interconnection exerts great influence on a reflection characteristic and an amplification characteristic of the amplifier. On the other hand, the inductance is optimized by adjusting a length and a width of the interconnection, thereby stabilizing a circuit and obtaining an excellent characteristic can be realized.
However, in the case that the number of fingers of a gate is increased in order to secure a large gate width, the plurality of sources are also needed. A length of an interconnection between the source and the back surface electrode, that is, a length to the via hole related to each source, is different for each source. Thus, the inductance that the interconnection between each source and the via hole has is also different for each source. In this case, since it is difficult to optimize the distance between the source and the via hole, the high frequency characteristic of the amplifier is degraded.
In order to prevent the high frequency characteristic from degrading, there is a method of fixing the length of the interconnection between each source and the via hole by arraying a plurality of unit FETs having one or two sources in parallel and arranging the via hole between the adjacent FETs. However, this method requires many via holes to be provided for the number of the sources. Thus, a size of the element becomes large. Further, since a length of an extraction connected to each gate and each drain is different for each unit FET, a phase difference is generated in output signals of each unit FET. When the plurality of output signals having the phase difference are subjected to vector composition, an amplitude of the output signals becomes smaller than a value for which the output signal from one FET is multiplied by the number of the unit FETs, and output as large as expected from the number of the unit FETs is not attained.
As another circuit structure, a circuit structure called an inverted micro strip line (MSL) is known. The inverted MSL is a structure in which an interconnection of a top layer is a reference potential layer, and is generally used in a surface mounting device. In the inverted MSL structure, the reference potential layer is arranged not on a back surface side of a substrate but on a surface side. Thus, a source of an FET arranged on the surface side of the substrate and a reference potential can be connected without using a substrate via hole of a large size. Further, by providing a via hole immediately above a source region, an inductance equivalently connected to the source region can be made zero.
However, in the case of providing a via structure immediately above the source region, since a distance between the source region and the via structure is almost zero, the inductance connected to the source region cannot be optimized to stabilize a circuit. In order to optimize the inductance, it is needed to adjust the distance between the source region and the via structure. As a result, similarly to a device provided with a reference potential pattern on a substrate back surface, in the case of increasing the number of fingers, the distance between the via structure and the source region cannot be optimized. Also, the problem that a phase difference is generated in the output signals among the plurality of FETs and large output cannot be attained in the case of increasing the number of fingers of the FET arises similarly to the case of a circuit configuration of providing the reference potential pattern on the substrate back surface.